FinFET transistor technology allows designers and fabricators to increase the level of integration, while providing ever smaller devices. FinFET transistors possess electrostatic advantages over planar transistors and are expected to be the technology of choice for high performance logic applications for current and future VLSI semiconductor technologies.
In conventional finFET technologies, the transistor employs a gate structure spanning across fin structures, enabling multiple fins to function simultaneously as one transistor. Similarly, the sources and drains of the ensemble of fins forming the transistor must also be electrically connected, or merged, by some method. However, methods to connect the finfet sources and drains currently practiced have been found to be challenged by high source/drain series resistance compared to that observed in planar transistors. Further, finFET transistors, because of the additional, non-planar topology that provides their electrostatic advantage, will have high levels of parasitic capacitance which needs to be minimized for overall technology performance. The primary parasitic capacitance component is between the source/drain structures and the gate structure.